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《Semiconductor Optoelectronics》 2011-04
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IP Core Design and Implementation for Rapid Multi-level 2D Integer Wavelet Transform

LI Qihu1,2,REN Guoqiang1,WU Qinzhang1,WANG Mingfu1(1.Institute of Optics and Electronics,Chinese Academy of Sciences,Chengdu 610209,CHN; 2.Graduate University of Chinese Academy of Sciences,Beijing 100149,CHN)  
To satisfy the demands of real-time and high-speed image processing system based on integer wavelet transform(DWT),according to the framework of lifting wavelet transform,an implementation method for 2D integer wavelet transform kernel design is proposed based on FPGA.In this architecture,both the row and column transformations can be processd concurrently by combining the data-extension procedure into the lifting-based DWT core and just three-line buffers are needed.Multiple pipeline registers are inserted into the architecture,reducing the power consumption and saving the memory space.So higher processing speed and hardware utilization are achieved.VHDL language is adopted in the design and the IP core is verified at 100 MHz clock frequency on XC2V30 FPGA.For the images with the size of 1 200×1 600 and depth of 12 bit,when the output time interval of two images is longer than the output time of three-line data,the synchronous process of multi-level IWT of the images can be achieved,without the need for dividing an image into small blocks.
【Fund】: 大科学工程国家遥感综合平台项目
【CateGory Index】: TN47
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