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《Semiconductor Technology》 2004-11
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Research of DFT for Board Level BS Chain Based on Boundary Scan Technology

LIU Ming-yuna, LI Gui-xiangb, ZHANG Xian-zhib, YANG Jiang-pingb(Air Force Radar Academy a.Group of Graduates; b.Department of RadarSystem Engineering,Wuhan 430019, China)  
Boundary-scan technology (BST) is a new and effective way of test and design-for-testability(DFT) for VLSI circuits. In the process of practical application of BST,we facedwith some problems to be resolved imminently, such as how to achieve the JTAG interconnectsamong the boundary scan (BS) devices that coming from different manufactories,belonging todifferent types and having different working voltages, as well as how to combine BS testing,in-system-programming (ISP) and in-system-emulation together,for resolving them,two designmethods of board level dynamic BS chin based on boundary scan technology are proposed withgood flexibility for DFT.
【CateGory Index】: TN407
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【Co-references】
Chinese Journal Full-text Database 10 Hits
1 CHENG Li, WANG Zhen-yu, GAO Ping, ZHU Jun(Institute of Electricity & Information, Jiangsu University, Zhenjiang 212013, China);The technologies and applications of DFT for VLSI[J];Semiconductor Technology;2004-05
2 YANG Xue-xian; ZHANG Qun-ying; HAN Yue-qiu (Department of Electronics Engineering, Beijing Institute of Technology, Beijing 100081);Boundary Scan Method for Radar System Level Test[J];JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY;2000-02
3 YU Yun-hua1,2, SHI Yin1 ( 1. Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China; 2. College of Information and Control Engineering, University of Petroleum, Dong Ying 257061, China );Research Progress on Strategy and Techniques of Fault Testing on Digital Integrated Circuits[J];Journal of Circuits and Systems;2004-03
4 Lo Dan;MCM Technique[J];ELECTRONIC COMPONENTS $ MATERIALS;1994-01
5 Wang Jingang Gong Xiaolin Su Qi;Application of JTAG Debugging Technology and ARM Emulator[J];Electronic Measurement Technology;2004-04
6 Li Zhengguang 1,2 , Lei Jia 2 (1. Huaihua University,Huaihua 418008, China; 2. Guilin University of Electronic Tecnology, Guilin 541004, China);Design for Testability and DFT Design Flow in EDA[J];Electronic Engineer;2004-04
7 Liu Hualin, Lei Jia, Yan xuelong (Guilin Institute of Electronic Industry, Guilin 541004, China);Design of the Verification Circuit Based on IEEE 1149.4 Standard[J];Electronic Engineer;2004-09
8 SONG Huibin,\ SHI Youhua (National ASIC system Engineering Research Center, Southeast University, Nanjing 210096, P.R.China);Testing Techniques of Low Power BIST for VLSI[J];Journal of Electron Devices;2002-01
9 Hu Zheng Wen Xisen (Department of Mechatronics and Instrumentation,NUDT,Changsha,410073);Mathematical Model of Boundary Scan Test[J];Journal of National University of Defense Technology;1999-05
10 Guo Xueren (Dept.of Electronic Engineering, Guilin 541004, China);The Boundary Scan test ——A Main Stream Test Technology for Complex MCM[J];Journal of Guilin Institute of Electronic Technology;2000-04
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