Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
Add to Favorite Get Latest Update

Interconnection Delay and Its Approximation for IC Layout Design

Chen Chunhong and Tang Pushan(Department of Electronic Engineering, Fudan University, Shanghai 200433)  
Interconnection delay has become a dominant factor for designing modern integrated circuits with high performance. We present a new approximation method for interconnection delay calculation. Based on Elmore delay model, this method uses RC tree structure of signal nets, and gives the tight lower bound of interconnection delay. It is shown that the proposed closed-form expression for interconnection delay plays an essential role in the timing-driven layout design.
【Fund】: “九、五”国家重点科研项目
【CateGory Index】: TN405
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
Chinese Journal Full-text Database 3 Hits
1 YU Hui,XU Yong-sheng,SHI Chun-qi,LAI Zong-sheng,TAO Yong-gang,JIN Wei,HONG Liang (Institute of Microelectronics Circuit & System, East China Normal University, Shanghai 200062, China);Study of Multiport Interconnection Delay[J];Journal of Electrical & Electronic Engineering Education;2005-04
2 LI Wen-shi~1, TANG Pu-shan~2, XU Qi-an~3, ZHANG Yan~1 (1. Dept. Microelectronics,Suzhou University, Suzhou,Jiangsu 215021; 2. Dept. Microelectronics, Fudan University, Shanghai 200433;3. Device Lab, Innosis Technology (Suzhou) Co., Ltd., Suzhou, Jiangsu 215021, P. R. China);Optimal Analysis and Simulation of Time Delay in Integrated Circuits[J];Microelectronics;2004-06
3 Chen Chunhong;Wang Jiayi;Long Zhongqi(College of Information Engineering,Zhejinang University fo Technology, Hangzhou 310032)Zhao Wenqing(Department of Electronic Engineering,Fudan University,Shanghai 200433);Developments in VLSI Interconnection Delay Analysis[J];JOURNAL OF ZHEJIANG UNIVERSITY OF TECHNOLOGY;1997-03
Chinese Journal Full-text Database 10 Hits
1 Ying Changsheng/Dept. of Computer Science & Technology,Tsinghua University, BeijingHong Xianlong/Dept. of Computer Science & Technology,Tsinghua University, BeijingWang Erqian/Dept. of Computer Science & Technology,Tsinghua University, Beijing;DRAFT——An Efficient Area Router Based on Global Analysis[J];Chinese Journal of Semiconductors;1988-06
2 Kong Tianming;Hong Xianlong and Qiao Changge(Dept. of Computer Set. & Tech., Tsinghua University, Beijing 100084)Received 22 July 1996, revised manuscript received 18 November 1996;VEAP: Efficient VLSI Placement Algorithm Based on Global Optimization[J];CHINESE JOURNAL OF SEMICONDUCTORS;1997-09
3 LI Chun\|hui, FAN Ming\|yu, ZHUANG Chang\|wen and YU Jue\|bang(The University of Electronic Science and Technology of China, Chengdu\ 610054, China)HUANG Jin(Ambow Corp., 2701 North Western Parkway, Santa Clara, CA 95051, USA)Received 26 April 1999, revi;Optimum Design of Power and Ground Topology Subject to Reliability and Noise Constraints[J];CHINESE JOURNAL OF SEMICONDUCTORS;2000-08
4 Hong Xianlong;Pan Li and Wang Erqian(Department of Computer Science and Technology,Tsinghua University,Beijing 100084);Via Minimization Algorithm for Double-Layer in VLSI and PCB[J];CHINESE JOURNAL OF SEMICONDUCTORS;1996-07
5 Yang Changling and Yan Xiaolang(Hangzhou Institute of Electronic Engineering, Hangzhou\ 210007);SERR: A Simulated Evolution Perfomance Driven Global Router[J];CHINESE JOURNAL OF SEMICONDUCTORS;1998-02
6 Zhuang Changwen, Fan Mingyu, Li Chunhui, Yu Juebang(Department of Optoelectronic Technology, University of Electronic Science and Technology of China, Chengdu 610054);Ant Colony Switchbox Router Based on Coordination Mechanism[J];CHINESE JOURNAL OF SEMICONDUCTORS;1999-05
7 Zhang Guoxiang (Dept. of physics Hubei Normal University, Huangshi,435002);The Application of Real-time Chip in the High Accuracy Time Control System[J];Journal of Chongqing Teachers College(Natural Science Edition);1998-S1
8 ZHANG Liang-zhen; LIU Hong; SHI Liang; QIN Wei(Department of Electrical Engineering and Information Science, Anhui University, Hefei, 230039 China);VLSI Placement Designed by Genetic Algorithm[J];JOURNAL OF CIRCUITS AND SYSTEMS;1999-03
9 ;Status and Prospects for Semiconductor IC Industry and Technology[J];Electronic Standardization & Quality;2003-04
10 SHI Chunqi, WU Jin, CHANG Changyuan, WEI Tongli (Microelectronic Center, Southeast University, Nanjing 210096 P.R.China);Study of LVS Methodology for Layout Physical Verfication[J];Journal of Electron Devices;2002-02
【Secondary References】
Chinese Journal Full-text Database 5 Hits
1 PAN Yin-song,LI Xiang-quan,ZHANG Cheng-wei,ZHANG Ren-fu,KONG Mou-fu(Key Laboratory of Optoelectronic Technology and System of Ministry of Education,Chongqing University,Chongqing 400030,China);Design of automatic data selector for microarray biosensor[J];Transducer and Microsystem Technologies;2009-08
2 LI Wen-shi1,2 TANG Chen2 (1 National ASIC System Engineering Research Center, Southeast University, )(2 Department of Microelectronics, School of Electronics and Information Engineering, Suzhou Univ., );Flash Quasi-4-bit ADC Design Simulation Based on Digital Circuits[J];China Integrated Circuit;2006-07
3 ;Design and Simulation for All-Digital ADC[J];China Integrated Circuit;2009-03
4 ZHANG Wen-bin~1, YUAN Bao-guo~1, WANG Sheng-guo~2(1.Shanghai Second Polytechnic University, Shanghai 201209,China;2.College of Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223-0001, USA);Application of Scaling in Simulation of High Order Interconnect Model[J];Computer Simulation;2005-03
5 YUAN Bao-guo1, WANG Sheng-guo2 (1.Shanghai Second Polytechnic University, Shanghai 201209, China; 2.University of North Carolina at Charlotte , Charlotte, NC 28223-0001, USA);Even Length Order RC Interconnect Model Reduction, Optimization and its Simulation[J];Journal of System Simulation;2006-07
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved