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《CHINESE JOURNAL OF SEMICONDUCTORS》 1997-07
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Interconnection Delay and Its Approximation for IC Layout Design

Chen Chunhong and Tang Pushan(Department of Electronic Engineering, Fudan University, Shanghai 200433)  
Interconnection delay has become a dominant factor for designing modern integrated circuits with high performance. We present a new approximation method for interconnection delay calculation. Based on Elmore delay model, this method uses RC tree structure of signal nets, and gives the tight lower bound of interconnection delay. It is shown that the proposed closed-form expression for interconnection delay plays an essential role in the timing-driven layout design.
【Fund】: “九、五”国家重点科研项目
【CateGory Index】: TN405
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【References】
Chinese Journal Full-text Database 3 Hits
1 YU Hui,XU Yong-sheng,SHI Chun-qi,LAI Zong-sheng,TAO Yong-gang,JIN Wei,HONG Liang (Institute of Microelectronics Circuit & System, East China Normal University, Shanghai 200062, China);Study of Multiport Interconnection Delay[J];Journal of Electrical & Electronic Engineering Education;2005-04
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【Co-references】
Chinese Journal Full-text Database 10 Hits
1 Ying Changsheng/Dept. of Computer Science & Technology,Tsinghua University, BeijingHong Xianlong/Dept. of Computer Science & Technology,Tsinghua University, BeijingWang Erqian/Dept. of Computer Science & Technology,Tsinghua University, Beijing;DRAFT——An Efficient Area Router Based on Global Analysis[J];Chinese Journal of Semiconductors;1988-06
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【Secondary References】
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1 PAN Yin-song,LI Xiang-quan,ZHANG Cheng-wei,ZHANG Ren-fu,KONG Mou-fu(Key Laboratory of Optoelectronic Technology and System of Ministry of Education,Chongqing University,Chongqing 400030,China);Design of automatic data selector for microarray biosensor[J];Transducer and Microsystem Technologies;2009-08
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