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《Chinese Journal of Semiconductors》 2003-04
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VLSI Thermal Placement Optimization Using Simulated Annealing

Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China)  
A placement scheme that considers both electrical performance requirements and thermal behavior for high performance VLSI chips is described.It is aimed at improving the substrate thermal distribution of a chip design without worsening the traditional design objects such as critical path delay and wire length very much.A useful placement method is developed using simulated annealing algorithm to optimize chip substrate thermal distribution.The simulation results show satisfied improvements of thermal distribution over the traditional placement algorithm with bearable increases of less than 4% in delay and total wire length of the final layout.
【Fund】: 国家自然科学基金资助项目 (批准号 :5 9995 5 5 0 -1)~~
【CateGory Index】: TN405
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【References】
Chinese Journal Full-text Database 4 Hits
1 Wang Nailong and Zhou Runde(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);A Novel Analytical Thermal Model for Temperature Estimation of Multilevel ULSI Interconnects[J];Chinese Journal of Semiconductors;2004-11
2 Xu Zheng 1,2 Yoshimura Takeshi2(1.School of Communication and Information Engineering,Shanghai University,Shanghai 200072;2.Graduate School of Information,Production and Systems,Waseda University,Kitakyusyu Japan);Multilevel floorplanning sesign for large-scale integrated circuits[J];Electronic Measurement Technology;2009-05
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Chinese Journal Full-text Database 1 Hits
1 Kong Tianming, Hong Xianlong and Qiao Changge(Department of Computer Science and Technology, Tsinghua University, Beijing\ 100084);POTIF: Efficient Power and Timing Driven Placement Algorithm[J];CHINESE JOURNAL OF SEMICONDUCTORS;1998-01
【Co-citations】
Chinese Journal Full-text Database 3 Hits
1 Zhang Yiqian,Xie Min,Hong Xianlong and Cai Yici(Department of Computer Science and Technology,Tsinghua University,Beijing 100084,China);Cross Point Assignment Algorithm Under Consideration of Very Long Nets[J];Chinese Journal of Semiconductors;2002-06
2 JIANG Xian yang,SHEN Xu bang,ZHANG Tian xu (Key Laboratory of Image Processing & Intelligent Control, Ministry of Education;Institute of Pattern Recognition & Artificial Intelligence, Huazhong Univ. Sci. & Technol., Wuhan, Hubei 430074, P.R.China);An Overview on the Design of Communication Specific IC's[J];Microelectronics;2001-05
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1 FU Gui-cui,GAO Ze-xi,ZOU Hang,WANG Dan-yan(Dept. of Systems Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100083, China);Thermal design of power component and optimal design of heat sink[J];Semiconductor Technology;2004-05
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【Secondary References】
Chinese Journal Full-text Database 5 Hits
1 HE Xu-shu,HUANG He,PEI Song-wei,BAO Su-su(School of Computer,South China Normal University,Guangzhou 510631,China);THERMAL ANALYSIS OF MULTILEVEL METAL ROUTING IN 0.1 μm ULSI TECHNOLOGY[J];Journal of South China Normal University(Natural Science Edition);2006-03
2 PEI Song-wei,HUANG He,HE Xu-shu,BAO Su-su(School of Computer,South China Normal University,Guangzhou,Guangdong 510631,P.R.China);Effects of Via on Temperature Distribution of Metal Wires[J];Microelectronics;2006-04
3 LIU Yan,BAI Yan,LI Jing(Institute of Information Engineering,PLA Information Engineering University,Zhengzhou 450002,China);Research of dispersed waveform and adventure in logic simulation[J];Computer Engineering and Design;2008-01
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5 SUN Qiang1,2,SUN Xing-qi3,MA Guang-sheng1(1.Dept.of Computer Science and Tech.,Harbin Eng.Univ.,Harbin 150001,China;2.Dept.of Computer Science and Tech.,Mudanjiang Teachers College,Mudanjiang 157012,China;3.The Second Artillery Qinzhou Warrant Officer School,Qingzhou 262500,China);High-level power optimization method for multiple supply voltage using the multi-objective genetic algorithm[J];Journal of Xidian University;2009-05
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