VLSI Thermal Placement Optimization Using Simulated Annealing

Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China)  

A placement scheme that considers both electrical performance requirements and thermal behavior for high performance VLSI chips is described.It is aimed at improving the substrate thermal distribution of a chip design without worsening the traditional design objects such as critical path delay and wire length very much.A useful placement method is developed using simulated annealing algorithm to optimize chip substrate thermal distribution.The simulation results show satisfied improvements of thermal distribution over the traditional placement algorithm with bearable increases of less than 4% in delay and total wire length of the final layout.

【Fund】： 国家自然科学基金资助项目 (批准号 :5 9995 5 5 0 -1)~~
【CateGory Index】： TN405

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