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《Journal of Semiconductors》 2008-03
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A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process

Zhu Zhangming,Qian Libo,and Yang Yintang(Institute of Microelectronics,Xidian University,Xi'an 710071,China)  
Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects.Applying function approximation and model order-reduction to the model,we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition.For various interconnect coupling sizes,the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process.This model can be used in computer-aided-design of nanometer SOCs.
【Fund】: 国家自然科学基金(批准号:60676009);; 国家杰出青年基金(批准号:60725415)资助项目~~
【CateGory Index】: TN432
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【Citations】
Chinese Journal Full-text Database 2 Hits
1 Yang Yuan,Gao Yong,and Yu Ningmei(Department of Electronic Engineering,Xi’an University of Technology,Xi’an 710048,China);Research on a Measurement Circuit for UDSM CMOS Process Parameter Variation[J];Chinese Journal of Semiconductors;2006-09
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【Co-citations】
Chinese Journal Full-text Database 3 Hits
1 YAO Lei2,CAI Jue-ping1,LI Zan2,ZHANG Hai-lin2,WANG Shao-Li2(1.Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory,Xi'an,Shaanxi 710071,China;2.State Key Laboratory of ISN,Xidian University,Xi'an,Shaanxi 710071,China);A Fault-Tolerant Routing Algorithm Based on BIST for 2D-Mesh Network-on-Chip without Using Virtual Channels[J];Acta Electronica Sinica;2012-05
2 OUYANG Yi-ming1,ZHANG Yi-dong1,LIANG Hua-guo2,HUANG Zheng-feng2(1.School of Computer and Information,Hefei University of Technology,Hefei,Anhui 230009,China;2.School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei,Anhui 230009,China);A Fault-Tolerant Design of Faults and Congestion-AwareRouter in Three-Dimensional Network-on-Chip[J];Acta Electronica Sinica;2013-05
3 HU Jing,MA Guangsheng,LI Donghai(College of Computer Science & Technology,Harbin Engineering University,Harbin 150001,P.R.China);Hierarchical Performance Analysis under Process Variations[J];Microelectronics;2008-04
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Chinese Journal Full-text Database 10 Hits
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