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《CHINESE JOURNAL OF SEMICONDUCTORS》 1998-01
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POTIF: Efficient Power and Timing Driven Placement Algorithm

Kong Tianming, Hong Xianlong and Qiao Changge(Department of Computer Science and Technology, Tsinghua University, Beijing\ 100084)  
Abstract A new efficient power and timing driven placement algorithm for very large scale small cell based ICs has been reported. Previously, very few approaches tend to handle power and timing issues simultaneously. Among previous approaches to timing driven placement, only one algorithm can handle large scale circuits, while it has three important problems: 1) the basic idea can only handle circuits whose timing graph is a DAG(Directed Acyclic Graph); 2) the delay model is rather simple, thus not appropriate for deep sub micron circuits; 3) it is not an all path based timing driven placement algorithm. Our algorithm can accurately control the longest path delay for very large scale circuits, while yielding excellent placement qualities and guaranteeing evenness of power distribution. Besides, our algorithm is the fastest for large scale circuits ever reported.
【Fund】: 国家攻关经费 高等学校博士学科点专项科研基金
【CateGory Index】: TN47
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【References】
Chinese Journal Full-text Database 3 Hits
1 Zhang Yiqian,Xie Min,Hong Xianlong and Cai Yici(Department of Computer Science and Technology,Tsinghua University,Beijing 100084,China);Cross Point Assignment Algorithm Under Consideration of Very Long Nets[J];Chinese Journal of Semiconductors;2002-06
2 Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);VLSI Thermal Placement Optimization Using Simulated Annealing[J];Chinese Journal of Semiconductors;2003-04
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【Co-references】
Chinese Journal Full-text Database 10 Hits
1 Li Jiang; Hong Xianlong; Qiao Changge and Cai Yici(Department of Computer Science and Technology, Tsinghua University, Beijing 100084);Cross Point Assignment Algorithm Based on Analysis of Net Type[J];CHINESE JOURNAL OF SEMICONDUCTORS;1997-08
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