Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
《Acta Scientiarum Naturalium Universitatis Pekinensis》 2007-01
Add to Favorite Get Latest Update

Hierarchical Network-on-Chip Design Method

WANG Hongwei 1)LU Junlin TONG Dong CHENG Xu(Microprocessor Research & Development Center,Peking University,Beijing,100871; 1))  
With the development of VLSI technology and increasing complexity of System-on-Chip applications,on-chip communication architecture design encounters some problems,such as throughput,power,signal integrity,latency and clock synchronization,Network-on-Chip(NoC)was introduced.With on-chip communication's specific pattern,it is of great significance to design hierarchical Network-on-Chip to improve communication performance and reduce hardware cost.This paper puts forward a hierarchical NoC design method.According to the technology and application requirements,researchers can generate several IP core subsets("cluster"),and design a NoC architecture as inter-cluster communication requirements.Experiments show with hierarchical NoC design method,this method can improve system performance efficiently,decrease hardware cost,and meet Quality-of-Service requirements at the same time.
【Fund】: 国家“863”高技术研究发展计划(2004AA1Z1010)资助项目
【CateGory Index】: TN47
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
【References】
Chinese Journal Full-text Database 1 Hits
1 SHEN Jian-liang1,YAN Ming1,LI Si-kun1,HOU Yi-fan2(1.School of Computer Science,National University of Defense Technology,Changsha 410073;2.Institute of Surveying and Mapping,Information Engineering University,Zhengzhou 450052,China);A Summary of Low Power Technology on NoC[J];Computer Engineering & Science;2009-S1
【Citations】
Chinese Journal Full-text Database 1 Hits
1 WANG Hong-wei,LU Jun-lin,TONG Dong,CHENG Xu (Microprocessor Research and Development Center,Peking University,Beijing 100871,China);Cluster Generation Algorithm for Hierarchical Networks-on-Chip Architecture[J];Acta Electronica Sinica;2007-05
【Co-references】
Chinese Journal Full-text Database 10 Hits
1 XU Ning-yi,LENG Xiang-lun,ZHOU Zu-cheng(Department of Electronics Engineering,Tsinghua University,Beijing 100084,China);SystemC-Based NoC Simulation Framework Supporting Heterogeneous Communicator[J];Semiconductor Technology;2006-04
2 Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);VLSI Thermal Placement Optimization Using Simulated Annealing[J];Chinese Journal of Semiconductors;2003-04
3 Zhu Zhangming,Qian Libo,and Yang Yintang(Institute of Microelectronics,Xidian University,Xi'an 710071,China);A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process[J];Journal of Semiconductors;2008-03
4 ZHU Xiao-hu1,CAO Yang1,2,WANG Li-wei1(1.School of Electronic Information,Wuhan University,Wuhan 430079,China;2.State Key Laboratory of Software Engineering,Wuhan University,Wuhan 430072, China);A Multilevel Congestion Control Routing Algorithm for Network-on-Chip[J];Journal of Beijing University of Posts and Telecommunications;2007-05
5 WANG Yanbo, WU Jin, CHANG Changyuan, Wei Tongli (Electronic Department, Southeast University, Nanjing,210096 P.R.China);Low-Power Design and Analysis For VLSI[J];Journal of Electron Devices;2002-02
6 MA Li-wei,SUN Yi-he (Institute of Microelectronics,Tsinghua University,Beijing,100084,China);Network-on-Chip Topology Optimizations:Floor-plan and Routing on Discrete Plane[J];Acta Electronica Sinica;2007-05
7 WANG Hong-wei,LU Jun-lin,TONG Dong,CHENG Xu (Microprocessor Research and Development Center,Peking University,Beijing 100871,China);Cluster Generation Algorithm for Hierarchical Networks-on-Chip Architecture[J];Acta Electronica Sinica;2007-05
8 FU Fang-fa,ZHANG Qing-li,WANG Jin-xiang,YU Ming-yan,SUN Yu-feng(Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China );Research on network on chip performance evaluation technology supporting various traffic distribution[J];Journal of Harbin Institute of Technology;2007-05
9 Guo Maozu Hong Yong Hong Jiarong (Dept.of Computer Science);Research and Implementation of the Dither Pattern Based on Simulated Annealing Algorithm[J];JOURNAL OF HARBIN INSTITUTE OF TECHNOLOGY;1997-03
10 ZHANG Henglong1,GU Huaxi2,WANG Changshan1 (1. School of Computer Xidian University,Xi'an China 710071; 2. State key lab of ISN Xidian University Xi'an China 710071);Research of Network on Chip Topology[J];China Integrated Circuit;2007-11
【Secondary Citations】
Chinese Journal Full-text Database 2 Hits
1 Lu Sanglu and Xie Li (Department of Computer Science, Nanjing University, Nanjing 210093) (State Key Laboratory for Novel Software Technology,Nanjing University,Nanjing 210093);LOBACA MODEL FOR LOAD BALANCE BASED ON CLUSTERS[J];JOURNAL OF COMPUTER RESEARCH AND DEVELOPMENT;1998-09
2 FENG Yong-Xin+, WANG Guang-Xing, LIU Zhi-Guo, JIANG Yue-Qiu (Research Center for Network and Communication, Northeastern University, Shenyang 110004, China);A Clustering Algorithm Applied to the Management of Mobile Ad Hoc Network[J];Journal of Software;2003-01
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved