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《Journal of Beijing University of Technology》 2007-10
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Design and Implementation of a Pipeline Model Machine Based on Verilog HDL

YI Xiao-lin PENG Yi-fan (College of Computer Science,Beijing University of Technology,Beijing 100022,China)  
In order to raise parallelism of executing instructions by model machine,this paper introduces the schema of designing a pipeline model machine.Using Verilog HDL,a pipeline model machine with parallelism of instructions which is combined with top-down method and DFA is implemented.This paper describes the schema and some algorithms of the pipeline model machine and simulates this machine in the end.The simula- tion results show that the model machine can process 4 instructions at the same time,and has the per-for- mances of pre-fetching instructions and bypassing.
【Key Words】: pipeline processing Verilog HDL descriptions microprocessor chips deterministic finite automation (DFA)
【CateGory Index】: TP302
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