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《Journal of Chongqing Institute of Technology(Natural Science Edition)》 2007-05
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Modeling and Optimized Design of Finite State Machine

CHEN Yong(Key Lab of Microelectronics Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,China)  
The circuits generated from the common Verilog HDL coding style are slow in speed,big in area,and serious in burr interference.Based on these characteristics,this paper presents an excellent and efficient manner described in Verilog HDL in the design of finite state machine.In addition,it introduces the modeling of finite state machines,and verifies with a synthesizable example the advantages of the design method of finite state machine in the area and power consumption.This method has a certain guiding significance in the design of very large scale integrated circuits.
【Fund】: 重庆市自然科学基金资助项目(渝科发技字[2004]55)
【CateGory Index】: TN431.2
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