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A high accuracy area and delay estimator for FPGA implementations

Wang Jiawei;Huang Zhihong;Gao Tongqiang;Yang Haigang;System on Programmable Chip Research Department,Institute of Electronics,Chinese Academy of Sciences;University of Chinese Academy of Sciences;  
The logic synthesis stage and physical synthesis stage will be repeated several times,when mapping the logic circuits to FPGA,to meet the area and timing constraints.In order to accelerate the traditional FPGA CAD flow,this paper presents a feed-forward neural network to predict the area and delay before the physical synthesis stage.Compared to the placement and routing results from VTR 7.0,the mean relative error(MRE)of the predicted area is 4.9%,and the mean relative error(MRE)of the predicted delay is 6.4%.This method works at early stage,but acquires a high accuracy compared to the related work.The estimator will help the designer reduce the design cycle and be capable of fully exploring the design space during the logic synthesis stage,thus improving the whole design quality.
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