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《Journal of Aerospace Power》 2011-01
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Design of the IP soft core of JTAG controller for electronic engine controller

YANG Sheng-kui1,ZHANG Tian-hong1,DENG Zhi-wei1,2(1.College of Energy and Power Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China;2.Aviation Motor Control System Institute,Aviation Industry Corporation of China,Wuxi 214063,China)  
It is feasible to realize on-line test by designing an intellectual property(IP) soft core of JTAG(joint test action group) controller which is based on filed-programmable gate array(FPGA).Through analyzing the state machine of test access port(TAP) controller and the principle of some application specific integrated circuit(ASIC) for boundary scan controller,the IP soft core of JTAG controller was designed for digital signal process(DSP) which was used in an electronic engine controller(EEC).Meanwhile the hardware of testing and verification system for boundary scan was designed,and the tests of main instructions were completed.This IP soft core,which can be used in many fields such as scan test and fault injection,can load the scan vector flexibly to realize on-line test.
【CateGory Index】: V233.7
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