Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
《Journal of South China Normal University(Natural Science Edition)》 2006-03
Add to Favorite Get Latest Update

THERMAL ANALYSIS OF MULTILEVEL METAL ROUTING IN 0.1 μm ULSI TECHNOLOGY

HE Xu-shu,HUANG He,PEI Song-wei,BAO Su-su(School of Computer,South China Normal University,Guangzhou 510631,China)  
Thermal model of multilevel metal interconnects is studied.Different dielectric material,metal wire separation,metal level separation and current density for impact of multilevel metal interconnects are calculated in detail.After considering these factors,the result indicates that the temperature of multilevel metal interconnects draws close to the actual temperature distribution much more.Furthermore,the theory foundation is presented so that the IC designer can design chip with higher performance and higher reliability.
【Fund】: 国家自然科学基金资助项目(60076013)
【CateGory Index】: TN47
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
【Citations】
Chinese Journal Full-text Database 3 Hits
1 Wang Nailong and Zhou Runde(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);A Novel Analytical Thermal Model for Temperature Estimation of Multilevel ULSI Interconnects[J];半导体学报;2004-11
2 RUAN Gang 1 and XIAO Xia 2 (1 ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China) (2 Center of Microtechnology,Technical University of Chemnitz,Chemnitz D-09107 ,Germany);Simulation of Thermal Performance of ULSI Inte rconnect System[J];半导体学报;2001-08
3 LIU Yan hong,\ ZHAO Yu,\ WANG Mei tian,\ HU Li zhong,\ WEI Xi wen (Dept.of Phys.,Dalian Univ.of Technol.,China);Physics 、structure and technology of the deep submicron MOS devices[J];半导体杂志;2000-01
【Co-citations】
Chinese Journal Full-text Database 8 Hits
1 GUO Jiayuan;LUO Xiangdong;Jiangsu Key Laboratory of ASIC Design,Nantong University;;Research on the Source Schottky Barrier SOI MOSFET[J];固体电子学研究与进展;2015-01
2 ZHANG Yan;DONG Gang;YANG Yintang;WANG Ning;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute,Xidian University;;Thermal Management of 3D Integrated Circuits Considering Horizontal Heat Transfer Effect[J];计算物理;2013-05
3 WANG Ning,DONG Gang,YANG Yintang,WANG Zeng,WANG Fengjuan,DING Can(Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute,Xidian University,Xian 710071,China);Thermoelectric Analysis of Interconnect Considering Via and Fringing Effects[J];计算物理;2012-01
4 Zhu Zhang-Ming,Xiu Li-Ping,and Yang Yin-Tang Microelectronics School,Xidian University,Xi'an 710071,China;A multilevel nano-scale interconnection RLC delay model[J];Chinese Physics B;2010-07
5 PEI Song-wei, HUANG He, HE Xu-shu, BAO Su-su (School of Computer, South China Normal University, Guangzhou 510631, China);Analysis of Hot Spots in ULSI Interconnect and Via Systems[J];微电子学与计算机;2007-04
6 HE Xu-shu,HUANG He,PEI Song-wei,BAO Su-su(School of Computer,South China Normal University,Guangzhou 510631,China);THERMAL ANALYSIS OF MULTILEVEL METAL ROUTING IN 0.1 μm ULSI TECHNOLOGY[J];华南师范大学学报(自然科学版);2006-03
7 PEI Song-wei,HUANG He,HE Xu-shu,BAO Su-su(School of Computer,South China Normal University,Guangzhou,Guangdong 510631,P.R.China);Effects of Via on Temperature Distribution of Metal Wires[J];微电子学;2006-04
8 YI Li-hua, ZENG Yun, YAN Min (Department of Applied Physics, Hunan University, Changsha Hunan, 410082, China);Breakthrough the Limit of Development of Silicon Technology[J];微电子技术;2003-02
【Secondary Citations】
Chinese Journal Full-text Database 3 Hits
1 Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);VLSI Thermal Placement Optimization Using Simulated Annealing[J];半导体学报;2003-04
2 RUAN Gang 1,XIAO Xia 2,ZHU Zhao min 1 (1 ASIC and System State Key Lab.,Fudan University,Shanghai 200433,China; 2 Center of Microtechnology,Technical University of Chcmnitz,D09107,Germany);Prospect on the Applicatoin of Low k Dielectric in ULSI[J];电子学报;2000-11
3 Zhang Dingkang; Yu Shan; Huang Chang(Xi'an Microelectronic Technology Inst.);Light-Doped Drain Technology for Submicron CMOS[J];微电子学与计算机;1994-01
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved