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B Code Demodulation Design Based on Nios Ⅱ Processor

LI Ling-mei1,2,WU Zhi-yong1,CUI Ming1 (1.Changchun Institute of Optics,Fine Mechanics and Physics,Chinese Academy of Sciences,Changchun 130033;2.Graduate University of Chinese Academy of Sciences,Beijing 100039)  
Pointing at the complexity of time unified and terminal system’s hardware architecture of the shooting range,this paper improves the original solution of the design technique of IRIG-B decodulation and system control,in terms of project implementation.Under the premise of observing GJB,it simplifies the hardware structure and innovates in design of system.It realizes the practice of integrated design time unified and terminal system based on FPGA’s Nios Ⅱembedded processor,and finishes decoding IRIG-B code(DC and AC).
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