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《Microelectronics》 2017-05
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A Type-Ⅰ Phase-Locked Loop with Low Reference Spur and High Power Supply-Noise Rejection Ratio

XI Na;ZHANG Jili;YE Yan;LIN Fujiang;Micro-Nano Electronic System Integration Center,University of Science and Technology of China;  
Based on GF 130 nm CMOS process,a high power supply-noise rejection ration and low reference spur type-Ⅰ PLL was designed.Compared with the charge pump phase-locked loop,the type-Ⅰ PLL had the disadvantages of small lock range and worse reference spur.In addition,the ring voltage controlled oscillator was analog circuit,and it was sensitive to the power supply noise.Noise in power line would deteriorate the oscillator output jitter performance.The reference spur and the power supply noise sensitive coefficient of the type-Ⅰ PLL had been reduced by employing a sample-hold circuit and a power supply voltage regulator.The simulation results showed that the proposed type-Ⅰ PLL could operate at a frequency range of 2.0-2.8 GHz.The reference spur was -66 dBc,and the power supply-noise rejection ratio(PSNR)was -24 dB while it consumed 9.7 mW from a 1.5 V supply.It occupied 0.009 mm~2.
【Fund】: 国家自然科学基金资助项目(61404123)
【CateGory Index】: TN911.8
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