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《JOURNAL OF TSINGHUA UNIVERSITY(SCIENCE AND TECHNOLOGY)》 1998-S1
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Tree based design approach for power/ground network

YU Hong, HONG Xianlong, QIAO Changge, CAI Yici Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China  
During the process of designing a cell based layout of very large scale integrated (VLSI) circuits, the deficiency and uneven power consumption have turned into obsession problems. This paper proposed a new method for the design of power/ground network according to the characteristics of gate array and standard cell circuits. Firstly, a concept of maximum free length is introduced; then the computing formula is developed and the power supply area of a chip layout is partitioned on the basis of maximum free length; finally, according to the result of partitioning, the topology of power/ground network is designed and the wire width is optimized.
【Fund】: 中国高等学校博士学科点专项科研基金资助项目
【CateGory Index】: TP301
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【Citations】
Chinese Journal Full-text Database 1 Hits
1 Kong Tianming, Hong Xianlong and Qiao Changge(Department of Computer Science and Technology, Tsinghua University, Beijing\ 100084);POTIF: Efficient Power and Timing Driven Placement Algorithm[J];CHINESE JOURNAL OF SEMICONDUCTORS;1998-01
【Co-citations】
Chinese Journal Full-text Database 3 Hits
1 Zhang Yiqian,Xie Min,Hong Xianlong and Cai Yici(Department of Computer Science and Technology,Tsinghua University,Beijing 100084,China);Cross Point Assignment Algorithm Under Consideration of Very Long Nets[J];Chinese Journal of Semiconductors;2002-06
2 Wang Nailong,Dai Hongyu and Zhou RundeProject supported by National Natural Science Foundation of China (No.59995550 1) Wang Nailong male,was born in 1977,PhD candidate.His research interests are low power CMOS circuit design and electrothermal simulation. Dai Hongyu male,was born in 1975,PhD candidate.His research interests are low power CMOS circuit design and embedded system design. Zhou Runde male,was born in 1945,professor and advisor for PhD candidates.His research interests are low power IC design and embedded system structure. Received 1 June 2002,revised manuscript received 4 November 2002○c 2003 The Chinese Institute of Electronics(Institute of Microelectronics,Tsinghua University,Beijing 100084,China);VLSI Thermal Placement Optimization Using Simulated Annealing[J];Chinese Journal of Semiconductors;2003-04
3 JIANG Xian yang,SHEN Xu bang,ZHANG Tian xu (Key Laboratory of Image Processing & Intelligent Control, Ministry of Education;Institute of Pattern Recognition & Artificial Intelligence, Huazhong Univ. Sci. & Technol., Wuhan, Hubei 430074, P.R.China);An Overview on the Design of Communication Specific IC's[J];Microelectronics;2001-05
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