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《Mini-micro Systems》 2001-05
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HARDWARE DESIGN'S FORMAL VERIFICATION BASED ON TEMPORAL LOGIC——MODEL CHECKING

GUO Jian1 DU Hui-min2 HAN Jun-gang1 HAO Ke-gang3 1 (ASIC Center,Xi'an instifute of post and teleommunications, Xian 710069,China) 2 (Compoter Department,Northwest Polytedmdogy University, Xian 710069,China) 3 (Compute Departnunt,Northwest Univ  
This article discusses the temporal logical application on the hardware verification, and analyzes the boolean function's expression -BDD in the computer. At last an example about hardware verification is given.
【Fund】: 国家自然科学基金资助! (NO69473 0 17)
【CateGory Index】: TP302
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