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THE IMPLEMENT OF SPEED ESTIMATION CORE BASED ON MRAS ALGORITHM

LIN Ping, HU Chang-sheng, LI Ming-feng, ZHANG Zhong-chao (College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China)  
The core in designing IC is growing more complex and abundant, so it requires higher specialization as its availability. Aiming to build up core library, in this paper, the advanced MRAS (Model Reference Adaptive System) scheme based speed sensorless drive of induction motor is presented first. Finally, a common core is created based on CPLD.10-bit system (the result of the estimated speed is a 10-bit digital) and a 12-bit one are presented, morever, their precisions and LC (Logic Cells) usages are compared. Experimental results are given to show its effectiveness. The result shows that designing a high capability AC control IC used this core as an embedded core with other CPU or DSP core can shorten efficiently the CPU processing time and constitute high performance close-loop control system.
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