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《Electronic Science and Technology》 2008-01
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ASIC Design of LD-CELP Coding

Yin Jinghua~1 Liu Qian~2 Wang Mingjiang~2 1.The School of Applied Science and Technology,Harbin University of Science and Technology,Harbin 150080,China; 2.Shenzhen Graduate School,Harbin University of Technology,Shenzhen 518055,China  
LD-CELP can satisfy all the performance requirements of 16Kbps algorithm,and has been widely applied in video conference systems,IP phones and other fields.According to this standard,the paper implements an RTL level design of speech coding using Verilog HDL.All the structures in the coding process are performed by DSP engine realized by Verilog HDL.Speech compression of the best coding index optimizes the consumption of bit.Physical test of coding system are implemented through FPGA verification,which shows that the coding system functions well,and is capable of real-time speech coding and decoding with good e- nough distinctiveness of voice.
【CateGory Index】: TN762;TN492
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【Co-citations】
Chinese Journal Full-text Database 1 Hits
1 HUANG De zhi,MA Jin wen (Institute of Mathematics ,Shantou University,Shantou,Guangdong 515063,China);An Improved Scheme of Vector Quantization in LD-CELP Speech Coding Algorithm[J];Acta Electronica Sinica;2001-10
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