Designing of Readout System for Missile-Loaded Data Based on FPGA and LVDS
ZHAO Yanggang;GUO Tao;HUANG Yugang;Science and Technology on Electronic Test and Measurement Laboratory,North University of China;
For on-board data back to the reading process,the parallel data transmission is difficult to complete synchronization clock at the same time,and the interaction between the parallel cable crosstalks,caused the parallel data read back cable length is generally limited to a few centimeters,so it needs to design a readout system for missileloaded data based on FPGA and LVDS. The system designed the FPGA as the core,used the FT245 BL as the control chip of USB,and adopted the LVDS technique that combined interface solution string and the drive chip. The combination of effective remote data transceiver. Experiments show that the data reading system can complete data remote transmission quickly and accurately without frame error or frame losing and has engineering practical value.