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《电子学报(英文)》 2018-05
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A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

YUAN Hengzhou;GUO Yang;LIU Yao;LIANG Bin;GUO Qiancheng;College of Computer Science,National University of Defense Technology;  
The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for1.25 Gb/s to 6.25 Gb/s wireline Ser Des transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential Charge pump(CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65 nm and 55 nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.
【Fund】: supported by the National Natural Science Foundation of China(No.61772540)
【CateGory Index】: TN911.8
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