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《Journal of Fudan University(Natural Science)》 2018-01
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An Efficient General Packing Method Based on CLB Internal Nets Sharing

YANG Zhao;YANG Meng;LAI Jinmei;State Key Laboratory of ASIC & Systems,Fudan University;  
To accommodate the increasingly complex structure of CLB(Configurable Logic Block)on modern FPGA chips,the process of the packing stage of existing CAD tools allows greater flexibility,which however leads to the marked increase of the amount of time spent in the packing stage.This paper intends to present a packing method named S-AAPack in view of CLB internal nets sharing.The method will first record the information of the nets sharing in CLB,which is related to the current packing process,then use the information to quickly recognize the illegal mappings,thereby greatly reduce the whole runtime.Experimental result shows that compared with the newest VTR7.0,S-AAPack enables the runtime of packing stage to be reduced by 1.83 times without changing the output quality in timing performance,area,etc.
【CateGory Index】: TN791
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