Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
《Industrial Control Computer》 2018-02
Add to Favorite Get Latest Update

Hardware Design of Real-time Median Filter Algorithm Based on FPGA

In order to ensure the real-time performance of median filter in image processing,the hardware design,Moselsim simulation and timequest timing analysis of median filtering algorithm are carried out by using Verilog language.The timing analysis shows that the hardware algorithm of median filter,which designed in this paper can reach the maximum working frequency up to 234.91 MHz.The result of the algorithm synthesis and simulation experiment on the Altera CYCLON II series EP2C35F484C6N FPGA platform show that,to process a 320x240 finger vein image data using the 3x3 template median filter working at 50 MHz frequency.It takes only 1.549 ms.Obviously meets the requirement of real-time of image processing.The hardware algorithm of median filter designed in this paper can be applied to ASIC chip design easily.
【CateGory Index】: TN791;TP391.41
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved