Development of Symbol Timing Recovery Circuit for Variable Rate QPSK Modem
Zhu Xiangdong Wang Shilin
Anovel approach to implement symbol timing recovery is presented which uses a hybrid digital phase locked loop (HDPLL).The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components. The baseband eye diagram drives a timing error detector to provide the timing error. This signal is independent of carrier phase information, thus permitting parallel symbol timing and carrier phase recovery operations.