Improved low-power optimization strategy targeting instruction bus
XU Burong, LI Xi, WEI Lianghui(Dept. of Computer Sci. & Tech., Univ. of Sci. & Tech. of China, Hefei 230027, China)
With the design of complier system and optimization for its low-power in compiling, the low-power optimization strategy for VLIW instruction bus is implemented in the compiler backend. The strategy reduces the number of voltage switch on instruction bus by rescheduling the generated binary code in horizon, which leads to system power reduction. The comparison experiments for software pipeline and super block scheduling are done, which shows that the optimization effect can be increased by more than 30% and has obvious relation to instruction level parallelism (ILP). At last, an enhancement method for the strategy is proposed based on ILP information. The statistics shows that the cost saved can reach up to 20%.