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《Computer Engineering and Applications》 2010-01
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Research of NCL circuits parallel processing architecture

CUI Ya-lei,DAI Zi-bin Institute of Electronic Technology,the PLA Information Engineering University,Zhengzhou 450004,China  
This paper proposes a framework of NCL circuits parallel processing for reducing the NCL data wave time.After the two dual-rail data waves through the parallel circuits,the next null data has been calculated,so,the data to data cycle time has been shortened.Taking the 4×4 multiplier for example,the circuits have been fabricated in 0.18 μm CMOS process.In the case of non-pipelining module,TDD has reduced 32.9% and in the case of 2 stage pipelining module,TDD has reduced 33.2%.
【CateGory Index】: TN402
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【Citations】
Chinese Journal Full-text Database 1 Hits
1 ZHONG Xiong-guang,RONG Meng-tian(IC and System Research Centre, Shanghai Jiaotong Univ., Shanghai 200030, China);A 32-bit Delay-Insensitive Asynchronous Pipelined Multiplier[J];Journal of Shanghai Jiaotong University;2004-11
【Co-citations】
Chinese Journal Full-text Database 1 Hits
1 WANG You-rui,WANG Lei,SHI Wei,DAI Kui,WANG Zhi-ying(School of Computer Science,National University of Defense Technology,Changsha 410073,China);Design and Implementation of the Asynchronous Sub-Word Parallel MAC Unit[J];Computer Engineering & Science;2009-01
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