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《Computer Engineering and Applications》 2010-03
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Implementation method of high-speed asynchronous FIFO using FPGA

HUANG Zhong-chao,ZHAO Yu-qian Department of Biomedical Engineering,School of Info -Physics and Geomatics Engineering,Central South University,Changsha 410083,China  
To overcome the metastability and ensure the validation of data transfer,the asynchronous First In First Out(FIFO) modules are often used to buffer data in systems with data transfers crossing clock domains.Because of the existence of the addressing pointers,which often adopt Gray-code counters,and the "full empty" generation logic in a usual asynchronous FIFO module,the signals passing two modules may suffer large delay.As a result,the working frequency of the whole module is limited. Based on a premise that th "efull" state will never occur in a high-frequency system,a method of implementing high speed asyn-chronous FIFO in FPGA is proposed.The focus on this way is that the "full" flag generation logic and redundant RAM depth are omitted,i.e.,only the "empty" flag is generated.So,the design of FIFO is simplified.The results from simulation and synthesis design show that the working speed of the whole module is greatly increased.
【Fund】: 高等学校博士学科点专项科研基金No.200805530185~~
【CateGory Index】: TN791
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【Co-citations】
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