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《Computer Engineering and Applications》 2010-03
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Implementation method of high-speed asynchronous FIFO using FPGA

HUANG Zhong-chao,ZHAO Yu-qian Department of Biomedical Engineering,School of Info -Physics and Geomatics Engineering,Central South University,Changsha 410083,China  
To overcome the metastability and ensure the validation of data transfer,the asynchronous First In First Out(FIFO) modules are often used to buffer data in systems with data transfers crossing clock domains.Because of the existence of the addressing pointers,which often adopt Gray-code counters,and the "full empty" generation logic in a usual asynchronous FIFO module,the signals passing two modules may suffer large delay.As a result,the working frequency of the whole module is limited. Based on a premise that th "efull" state will never occur in a high-frequency system,a method of implementing high speed asyn-chronous FIFO in FPGA is proposed.The focus on this way is that the "full" flag generation logic and redundant RAM depth are omitted,i.e.,only the "empty" flag is generated.So,the design of FIFO is simplified.The results from simulation and synthesis design show that the working speed of the whole module is greatly increased.
【Fund】: 高等学校博士学科点专项科研基金No.200805530185~~
【CateGory Index】: TN791
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Chinese Journal Full-text Database 3 Hits
1 Xiong,Hongbing Chen,Qi;Asynchronous FIFO Design and Implementation Based on FPGA[J];;2006-17
2 YU Hai, FAN Xiao-ya (Aviation Microelectronics Center, Northwestern Polytechnical University, Xi'an 710072, China);Research and Implementation of Asynchronous FIFO Based on FPGA[J];Microelectronics & Computer;2007-03
3 YANG Jun,KONG Bing,SONG Ke-jian,YIN Hang(College of Information,Yunnan University,Kunming 650091,China);Design of high-speed asynchronous FIFO memory based on VHDL[J];Journal of Yunnan University(Natural Sciences Edition);2007-06
Chinese Journal Full-text Database 10 Hits
1 Taiyuan University of Science and Technology Xie Wenhua, Gao Wenhua;Problems and Solutions for Asynchronous FIFO Design Based on FPGA[J];Microcontrollers & Embedded Systems;2009-08
2 Pan Jianguo Que Peiwen Lei Huaming (Department of Instrument Science and Engineering,Shanghai Jiao Tong University,Shanghai 200240);Design of data acquisition system with high speed and large capacity based on FPGA[J];Electronic Measurement Technology;2008-09
3 REN Yong-feng,HU Zhen-liang,Li Sheng-kun(National Key Laboratory for Electronic Measureent Technology,North University of China,Taiyuan 030051,China);Design of multi-channel digital signal collecting module based on FPGA[J];International Electronic Elements;2008-05
4 Xiao Jingxian Dai Yawen(WuHan University of Technology School of Science,Wuhan 430070);Implementation of asynchronous FIFO buffer based on FPGA[J];Electronic Measurement Technology;2009-11
5 YAO Jing,ZHENG Jian-yong,MEI Jun,WANG Fei(School of Electrical Engineering,Southeast University,Nanjing 210096,China);Realization of Data Receiving and Processing Module in Merging Unit Based on FPGA[J];Electrotechnics Electric;2009-07
6 SU Jing, YANG Zhi-yi~1 HAN Zhi-xia~2 (Software and Microelectronics College, Department of Computer~1 of Northwestern Polytechnical University, Xi’an 710068, P.R.China; Baoji School of Laterature and Science~2, Baoji 721007,P.R.China);Design and Realization of NC System LCD Controller Based on FPGA[J];Science Technology and Engineering;2007-05
7 LIU Liansheng,JIANG Jianfei(Civil Aviation University of China,Tianjin 300300,P.R.China);Design of Multi-Channel ARINC429 Interface IC Based on FPGA[J];Microelectronics;2010-01
8 HU Jian-sheng1,LUO Wei-bing1,QIAN Yuan2(1.Derpartment of Communication Engineering,Institute of Chinese People’s Armed Police Forces Engineering,Xi’an 710086;2.Air Force Engineering University,Xi’an 710077);Design of Embedded TFT-LCD Controller[J];Computer Engineering;2010-05
9 DUAN Su-rong ① ,ZHUANG Sheng-xian ② (①The school of information science and technology, Southwest Jiaotong University, Chengdu 610031, China; ②The school of electrical engineering, Southwest Jiaotong University, Chengdu 610031, China);Design and Realization of Inner Couplers FIFO Full Duplex UART[J];Communications Technology;2010-02
10 WANG Shui-yu,WANG Xiao-fen(Xi′an University of Technology,Xi′an 710048,China);Design of customer-counting statistic system based on FPGA and PC[J];Journal of Shaanxi University of Technology(Natural Science Edition);2010-01
【Secondary Citations】
Chinese Journal Full-text Database 3 Hits
1 (Information Engineering Institute of Information Engineering University of PLA,450003)yan lei;The Realization of Manchester Data Transform System Based on FPGA[J];;2006-02
2 Sun Huajin, Gao Deyuan, Fan Xiaoya, Zhang Shengbing (Aviation Microelectronic Center, Northwestern Polytechnical University, Xi′an 710072, China);On Designing for Chinese Use a BIU (Bus Interface Unit) of a 32-bit RISC[J];Journal of Northwestern Polytechnical University;2004-03
3 ;Transfering Data by Asynchronous FIFO between Clock Domains[J];Electronic Design & Application World;2004-08
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