Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
《Computer Engineering》 2006-01
Add to Favorite Get Latest Update

Design of DDR SDRAM Controller in Video Decoder

LIU Yang,LIN Zhenghui(EE Department,Shanghai Jiaotong University,Shanghai 200030)  
This paper introduces a high-speed DDR SDRAM controller for video decoder SoC.DDR control unit and system local bus arbitrate unit are merged in one controller harmoniously.According to the requirement of the whole system and the characteristic of DDR SDRAM,the paper presents the optimized solution in structure and timing aspect.And it also presents the strategy of FPGA prototype verification and the implementation result on FPGA ASIC.
【Fund】: 国家“863”计划基金资助项目(2002AA1Z1190)
【CateGory Index】: TN76
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved