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《Microelectronics》 2003-01
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A 1.25 Gbps CMOS Serializer/Deserializer for Ethernet

GUO Yawei, ZHANG Zhanpeng, ZHANG Yimin, QIU Zujiang, YANG Lianxing33, P R China; 2 Vaishali Semiconductor LLC,Campbell, CA, USA, 95008; 3 Shanghai Minqin Electronic Technology Co, Ltd, Shanghai,200001, P R China)  
A monolithic 125 Gbps Serializer/Deserializer (Serdes) for Gigabit Ethernet is fabricated in 035 μm CMOS process with double polysilicon and triple metal layers This transceiver is compatible with the fiber channel physical layer (FC0) standard The critical cell of this chip,serializer deserializer, is simpler and smaller than the previously reported circuit The highspeed serial data has a random jitter only half of the previous reports Loop filters for the phase locked loop are integrated into the chip 
【CateGory Index】: TN929.11
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【References】
Chinese Journal Full-text Database 1 Hits
1 HUANG Jia(Department of Physics and Electronic Information Science,Guangxi Teachers Education University,Nanning 530023,China);The Design of 2.5Gbps High Speed Serializer for PCI Express[J];Journal of Guangxi Teachers Education University(Natural Science Edition);2009-03
【Co-references】
Chinese Journal Full-text Database 10 Hits
1 Zeng Xiaojun,Li Tianwang and Hong ZhiliangZeng Xiaojun male,was born in 1968,PhD.His main research area includes digital signal processing and high speed digital circuit design. Li Tianwang male,was born in 1968,PhD.His main research area includes mixed signal and RF circuit design. Hong Zhiliang male,was born in 1946,PhD,professor,advisor of PhD student,involved in research of VLSI design,special interest in high speed analog and mixed signal circuit design. Received 14 May 2002,revised manuscript received 7 July 2002○c 2003 The Chinese Institute of Electronics(Department of Electronic Engineering,Fudan University,Shanghai 200433,China);Design of a 1V,19GHz CMOS Frequency Divider[J];Chinese Journal of Semiconductors;2003-04
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3 Huang Lin,Guo Gan,Ye Jinghua,Chen Yihui,and Hong Zhiliang(Department of Microelectronics,Fudan University,Shanghai 200433,China);CMOS Serial Transceiver with Half-Rate Architecture[J];Chinese Journal of Semiconductors;2005-01
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7 ZHAO Wen-hu, WANG Zhi-gong, FEI Rui-xia, ZHU En, WU Wei ( Institute of RF & OE ICs, Southeast University, Nanjing 210096, China );Study on 8B/10B Encoding and Decoding Method Based on Logic Analysis for Fiber Communication[J];Journal of Circuits and Systems;2003-02
8 DAI Ju-feng, HE Chuan-feng, MAO Lu-hong ( School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China );Study on a new implementing method of 8B/10B encoding and decoding for fiber communication[J];Journal of Circuits and Systems;2005-02
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