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《Microelectronics》 2008-01
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A Novel Low Jitter and Fast Locking Clock Stabilizer

ZHANG Feng-jiang1,2,ZHOU Shu-tao2,3,LI Ru-zhang2,3,ZHANG Zheng-fan2,3 (1.Chongqing University of Posts and Telecommunications,Chongqing 400065;2.National Laboratory of Analog IC's,Chongqing 400060;3.Sichuan Institute of Solid State Circuits,CETC,Chongqing 400060,P.R.China)  
A novel low-jitter fast-locking clock stabilizer is presented.By detecting the rising edge of the input clock signal,the circuit generates two peak pulses,one of which is exactly delayed by half cycle,to form a stable clock with low jitter.The circuit was simulated based on 0.35 μm standard CMOS technology.At input clock rate of 100 MSPS,the circuit has a peak-to-peak clock jitter of 56 fs,and its power dissipation is only 0.35 mW.
【CateGory Index】: TN492
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【References】
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