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《Microelectronics》 2009-01
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Design of Low Jitter Voltage Controlled Oscillator in Phase Locked Loop

LIANG Yan,WU Jin(Institute of Integrated Circuit,Southeast University,Nanjing 210096,P.R.China)  
The PLL system noise and phase noise of the VCO were investigated.Based on the investigation,a low phase noise VCO containing a 2-stage differential ring oscillator was designed using CSMC's 0.5 μm CMOS process.Results from Spectre RF simulation showed that the VCO had a frequency range from 524 MHz to 1.1 GHz,a peak gain,KVCO,of-636.7 MHz/V,a VCO phase noise of-116.2 dBc/Hz at 1 MHz offset for 900 MHz oscillating frequency,and a power consumption of 21.2 mW.And system simulation showed that the VCO phase noise contribute to PLL jitter by less than 1 ps.
【CateGory Index】: TN752
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Chinese Journal Full-text Database 1 Hits
1 CAI Zhimin1,2,CHEN Yingmei1,LI Zhiqun1,ZHANG Li1,LI Wei1 (1.Institute of RF-& OE-ICs,Southeast University,Nanjing,Jiangsu 210096,P.R.China;2.Information and Electronics Engineering Institute,East China Institute of Technology,Fuzhou,Jiangxi 344000,P.R.China);A Low Power Voltage Controlled Oscillator for RF Receiver in GPS[J];Microelectronics;2009-06
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