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《Microelectronics》 2009-01
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A Low-Power RF CMOS Charge Pump PLL

ZHOU Haifeng,HAN Yan,DONG Shurong,HAN Xiaoxia,CHENG Weiwei(1.Institute of Microelectronics and Photoelectronics,Zhejiang University,Hangzhou 310027,P.R.China)  
A phase-locked loop(PLL) based on voltage controlled oscillator(VCO) with P-type CSL(Current Steer Logic) structure was presented.A pre-charge mode was used in phase/frequency detector to realize high speed and dead zone free,etc.The topology of the circuit was also enhanced to equalize the depths of charge and discharge currents,which improved the circuit matching.In order to expand the tuning range of the PLL,a 1.8 V power supply was used in the charge pump module,while a 3.3 V power supply was used for VCO module.This circuit was implemented in a 0.18 μm 1P6M CMOS technology,and the core chip occupied an area of 750 μm×400 μm.Test results showed that the PLL operated in the frequency range between 940 MHz and 2.23 GHz,with a power consumption less than 15.2 mW.
【Fund】: 国家高技术研究发展(863)计划基金资助项目(2008AA04Z309)
【CateGory Index】: TN402
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