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《Microelectronics》 2016-01
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A FPGA-Based Time-to-Digital Converter with Shifted Clock Sampling Technique

WANG Wei;LI Jie;DONG Yongmeng;XIONG Pinbo;ZHOU Hao;YUAN Jun;WANG Guanyu;YANG Zhenglin;CHEN Dan;College of Electronics Engineering,Chongqing Univ.of Posts and Telecommunications;Chongqing Lotus Silicon Electronics Technology Ltd.Co.;  
A kind of time-to-digital converter(TDC)was designed with shifted clock sampling technique in Xilinxs general purpose Virtex-5field programmable gate array(FPGA).The clock management tile(CMT)was utilized to produce 16-channel fixed phase-shifted signals,then was combined with 16D-type flip-flops to sample and quantify the input signal.Compared with the traditional TDC design methods,such as tapped delay lines,the proposed circuit needed lower resources,and was more stable.The simulation results showed that the time accuracy was as high as 64 ps,and less than 20% of DCM and PLL resources in FPGA were used.The integral nonlinearity(INL)and differential nonlinearity(DNL)characteristics of the designed TDC were both less than 0.3LSB.
【Fund】: 国家自然科学基金资助项目(61404019)
【CateGory Index】: TN791
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