Full-Text Search:
Home|Journal Papers|About CNKI|User Service|FAQ|Contact Us|中文
《Journal of Shanghai Jiaotong University》 2013-01
Add to Favorite Get Latest Update

Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor

HAN Xing,JIANG Jiang,FU Yu-zhuo,ZHOU Chuan,LIU Zi-yang,YANG Kai-kai(School of Microelectronics,Shanghai Jiaotong University,Shanghai 200240,China)  
A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced.According to the locality principle,both the hardware support,including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol,and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor.This paper also introduced the simulation platform for dynamically reconfigurable many-core processor,which is developed based on system level simulator Gem 5.The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented.The simulation result proves the improvement for performance of the many-core processor.
【Fund】: 国家高技术研究发展计划(863)项目(2009AA012201);; IBM共享大学研究项目(SUR201102X)
【CateGory Index】: TP368.1
Download(CAJ format) Download(PDF format)
CAJViewer7.0 supports all the CNKI file formats; AdobeReader only supports the PDF format.
©2006 Tsinghua Tongfang Knowledge Network Technology Co., Ltd.(Beijing)(TTKN) All rights reserved