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《Journal of Shanghai Jiaotong University》 2013-01
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Design for Silicon Debug of Integrated Circuit by Reusing Test Logic

ZHANG Ming,GAO Jun,ZHANG Min-xuan(College of Computer,National University of Defense Technology,Changsha 410073,China)  
Test logic is often reused by silicon debug during design stage of IC.Based on reusing test logic,two improved structures for silicon debug were proposed,one is that scanning registers in short chains to speedup accesses of focused registers,another is that adding asynchronous debug ports for memory build-in self-test(MBIST) controller,which accelerates accesses of static memory and reduces difficulties of physical design.The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost,and makes debug operations faster.
【Fund】: 核高基重大专项(2009ZX01028-002-002);; 国家自然科学基金项目(61202122);; 信息保障技术重点实验室基金(KJ-11-04)资助
【CateGory Index】: TN407
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