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《Journal of Shanghai Jiaotong University》 2013-01
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Reliability-Aware Optimization for Task Mapping in Network-on-Chip

LIU Ting,WU Yao-yi,FU Yu-zhuo(School of Microelectronics,Shanghai Jiaotong University,Shanghai 200240,China)  
To meet the increasing demands on reliability of specific applied areas,this paper presented RaNMAP,a reliability-aware task mapping algorithm for network-on-chip(NoC) applications.The RaNMAP was developed from an existing greedy heuristic mapping algorithm called NMAP,by adding a new scheme to define fault tolerant technique based communication cost and set reliability as the constraint.The algorithm was applied with NoC task benchmarks and demostrated an overall reliability improvement under most simulaition conditions.The analysis results show that RaNMAP offers an effective framework for high Abstract level fault tolerance aware design and evaluation in NoCs.
【Fund】: 国家高技术研究发展计划(863)项目(2009AA012201);; Cisco大学研究计划(2011-90403(3696))资助项目
【CateGory Index】: TN47
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【Secondary Citations】
Chinese Journal Full-text Database 4 Hits
1 YUE Pei-pei1,LIU Jian1,SHEIKH Anjum1,2,CHEN Jie1(1.Institute of Microelectronics,Chinese Academy of Sciences Haidian Beijing 100029;2.COMSATS Institute of Information Technology Islamabad Pakistan);Enumeration-Based Path Allocation Algorithm in NoC Mapping[J];Journal of University of Electronic Science and Technology of China;2008-01
2 Yang Wei, Li Qiqiang (School of Control Science and Engineering, Shandong University, Jinan 250061, China);Survey on Particle Swarm Optimization Algorithm[J];Engineering Science;2004-05
3 ZHOU Wenbiao1,2,ZHANG Yan1,MAO Zhigang2(1.SoC Research Centre of Shenzhen Graduate School,Harbin Institute of Technology,Shenzhen 518055;2.Microelectronics Centre,Harbin Institute of Technology,Harbin 150001);Low Power Adaptive Data Protection for Network on Chip[J];Computer Engineering;2006-22
4 GAO Ming-lun~(1,2),DU Gao-ming~1(1.VLSI Research Institute,Hefei University of Technology,Hefei,Anhui 230009,P.R.China; 2.VLSI Research Institute,Nanjing University,Nanjing,Jiangsu 210093,P.R.China);NoC: Next Generation Mainstream Architecture for Integrated Circuits[J];Microelectronics;2006-04
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