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《Journal of Shanghai Jiaotong University》 2013-01
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A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor

WANG Di1,BAI Han2,ZHAO Tian-lei1,TANG Yu-xing1,DOU Qiang1(1.College of Computer,National University of Defense Technology,Changsha 410073,China; 2.Jiangsu Unit,Chinese People's Armed Police Force,Nanjing 210036,China)  
By utilizing silicon via's characteristics such as short delays and less power consumption,this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies.By analyzing the experimental data the paper proves 3DE-Mesh's function and scalability.The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.
【Fund】: 国家“核高基”科技重大专项(2011ZX01028-001-001 2009ZX01028-002-002)
【CateGory Index】: TN47
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