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《Journal of Shanghai Jiaotong University》 2013-01
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Low Power Design of a Multi-Core Processor Chip

GAO Jun,WANG Yong-wen,GUO Wei,HUANG An-wen(College of Computer,National University of Defense Technology,Changsha 410073,China)  
In order to implement low power design of Cool Symmetry Processor(CSP) which is a high frequency multi-core processor chip,three techniques are proposed for power reduction based on CSP structure,that is interval power gating,dynamic frequency scaling based on throughput and hierarchical clock gating.The results of experiment show the three low power techniques reduce CSP chip power effectively.The interval power gating solves leakage power,the dynamic frequency scaling based on throughput and hierarchical clock gating can control dynamic power.
【Fund】: 国家自然科学基金项目(61170045 61103011);; 国家“核高基”重大专项资助项目(2009ZX01028-002-002)
【CateGory Index】: TN47
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【Citations】
Chinese Journal Full-text Database 2 Hits
1 WANG Bing, WANG Qin, PENG Rui-hua, FU Yu-zhuo(School of Microelectronics, Shanghai Jiaotong Univ., Shanghai 200030, China);Design of a Low Power DSP with Distributed and Early Clock Gating[J];上海交通大学学报(英文版);2007-05
2 LU Jun ming, LIN Zheng hui (LSI Research Inst., Shanghai Jiaotong Univ., Shanghai 200030, China);Average Power Estimation in CMOS Circuit with Least Square Method[J];Journal of Shanghai Jiaotong University;2002-03
【Secondary Citations】
Chinese Journal Full-text Database 1 Hits
1 WANG Tian, CHEN Jian, FU Yu zhuo (IC and System Research Center, Shanghai Jiaotong University, Shanghai 200030, China);Custom Design of 32-Bit Fast Multiplier[J];Mini-micro Systems;2005-02
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