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《Journal of Shanghai Jiaotong University》 2013-01
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A Synthesizable Pseudo-Random Functional Verification Method for Cache

ZHANG Jian-min,ZHANG Jun,XIA Jun,PANG Zheng-bin,XU Wei-xia(College of Computer,National University of Defense Technology,Changsha 410073,China)  
For the Cache in the microprocessors,a synthesizable pseudo-random functional verification method was proposed.This method was applied in the real chips,and was compared with the pseudo-random verification method on software simulation in performance.The results show that the method is faster by about three orders of magnitude,and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.
【Fund】: 国家自然科学基金项目(61103083 61133007);; 国家高技术研究发展计划项目(863)项目(2012AA01A301)资助
【CateGory Index】: TP333
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【Citations】
Chinese Journal Full-text Database 6 Hits
1 Shen Haihua1,2, Wang Pengyu1,2,3, Wei Wenli1,2,3, and Guo Qi1,2,3 1(Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing 100190) 2(Research Center of Microprocessor Technology, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190) 3(Graduate University of Chinese Academy of Sciences, Beijing 100049);A Coverage Directed Test Generation Platform for Microprocessors Using Genetic Approach[J];Journal of Computer Research and Development;2009-10
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【Co-citations】
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1 Guo Qi1,2,3) 1)(State Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190) 2)(Graduate School of Chinese Academy of Sciences,Beijing 100049) 3)(Loongson Technologies Corporation Limited,Beijing 100190);Online Filtration of Stimuli for Microprocessor Verification[J];Journal of Computer-Aided Design & Computer Graphics;2012-05
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