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《Journal of Shanghai Jiaotong University》 2014-10
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Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application

CAO Peng;MEI Chen;LIU Bo;National ASIC System Engineering Research Center,Southeast University;  
In order to optimize the data flow of coarse grain reconfigurable architecture REMUS-II(Reconfigurable Multimedia System2)for high performance media decoding,a novel memory sub-architecture of on-and off-chip memory was proposed by analyzing the data access pattern for multimedia application.For on-chip memory,the 2D-data and transpose transfer technique was employed to improve the data transfer efficiency by 69.6%and 15.1%on average,respectively.For off-chip memory,the block buffer was implemented to reduce the reference frame accesses with a 37%reduction of accessing time on average.With the memory hierarchy optimization,REMUS-II can achieve real-time H.264 high profile and MPEG2 high level decoding with a definition of 1 980pixel×1 080 pixel at 200 MHz clock frequency.
【CateGory Index】: TP333
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【Co-citations】
Chinese Journal Full-text Database 3 Hits
1 Cao Peng;Yang Jinjiang;Mei Chen;National ASIC System Engineering Research Center,Southeast University;;Parallel FFT algorithm implementation based on coarse-grained reconfigurable architecture[J];Journal of Southeast University(Natural Science Edition);2013-06
2 Liu Bo;Xiao Jian;Cao Peng;Yang Miaomiao;National ASIC System Engineering Research Center,Southeast University;;Data cache structure and management strategy optimization of reconfigurable system for multimedia applications[J];Journal of Southeast University(Natural Science Edition);2014-06
3 LIU LeiBo;WANG YanSheng;YIN ShouYi;ZHU Min;WANG Xing;WEI ShaoJun;Institute of Microelectronics, Tsinghua University;National Laboratory for Information Science and Technology, Tsinghua University;;Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture[J];中国科学:信息科学(英文版);2014-10
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