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《Journal of Data Acquisition and Processing》 2011-04
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Design of IP Core for JPEG Decodeding Based on SOPC

Xu Zhijun1,Zhang Shiwei2,Xu Guanghui1(1.Institute of Communication Engineering,PLA University of Science and Technology,Nanjing,210007,China;2.Department of Communication Engineering,Chongqing Communication Institute,Chongqing,400035,China)  
To put forward a design of IP core for realizing JPEG decoding in system on programmable chip(SOPC) leads to large amount of JPEG decoding calculation operated through hardware.The embedded processor participates in a small part of work,thus the design improves the decoding speed of JPEG.The theory of JPEG decoding is analyzed,and several modules are constructed which are composed of Huffman decoding,inverse quantization module,and inverse discrete cosine transform module with hardware language.The design of JPEG decoder is accomplished.The emulational experiments and test indicate that the design of IP core for realizing JPEG decoding in SOPC perform well with high efficient flexibility and low cost.
【Fund】: 江苏省自然科学基金(BK2009059)资助项目
【CateGory Index】: TN47
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