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《Journal of Data Acquisition and Processing》 2011-05
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FPGA Implementation of Data Acquisition and Timing Mismatch Compensation for TIADC System

Zhang Shangliang,Zou Yuexian(Advanced Digital Signal Processing Laboratory,Peking University,Shenzhen,518055,China)  
The special multichannel structure of the front-end of the time-interleaved analog-to-digital converter(TIADC) introduces the channel mismatches unavoidably,and brings forth big challenges of the digital backend system design for the multi-channel high speed data capturing,processing and storing.Using the FPGA and SoPC technologies,the research focuses on the design for modular general-purpose TIADC digital backend system to overcome the above mentioned technical challenges.The digital backend system is designed to provide the functions of multichannel high-speed time-interleaved data capture,the multichannel Lagrange interpolating digital background compensation for the timing mismatch,data storage and data transmission after compensation.Analysis shows that the digital backend system proposed in this paper has well-defined characteristics of expansibility,and it can be used to design the different TIADC systems with different structures.The experimental evaluation is carried out for a designed digital backend system of a 4*80 MS/s 12 bit TIADC system.The experimental results prove its working stability and show a 25 dB SFDR performance improvement by using the sixth order multichannel Lagrange interpolating filter.
【Fund】: 国家自然科学基金(60775003)资助项目
【CateGory Index】: TN792
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