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《Computer Engineering and Design》 2010-01
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Bounded model checking of timed automata based on Yices

WANG Xiao-liang1,2(1.State Key Laboratory of Computer Science,Institute of Software,Chinese Academy of Science,Beijing 100190,China;2.Graduate University,Chinese Academy of Science,Beijing 100049,China)  
To avoid encoding variants in the model into boolean type in the process of bounded model checking(BMC) and preprocessing clocks for timed automata(TA),a method of BMC for timed automata based on SMT tools is presented.Timed automata is transformed into logic formula directly which is recognizable for SMT tools,and then takes advantages of the ability of SMT tools,which is SMT tool could solve the formula which includes variants of integral or real,to do checking works.It is demonstrated by experimental results that,for some verification of reachability,the presented method has better performance.
【CateGory Index】: TP301.1
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