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《Electronic Test》 2014-01
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SDRAM controller design and implementation

Yu Ming;Gao Jian;Beijing Institute of Auto-Testing Technology;  
This project is based on SDRAM controller design.Used in automatic test equipment test vector generator,it controls of SDRAM and the outside world for communication and data transmission.SDRAM memory is accessed by burst mode.Its working principle is that SDRAM add synchronization in the existing standard dynamic memory control logic(a state machine).Using single system clock syncs all the address of the data and control signals.With points under the conditions of the state machine as the main line,three modules respectively complete command code refresh, command execution,as well as the data path selection function. The data input,and then read back. Design good and error signals,determine success or failure of reading and writing.Finally,take a detail view of the reading and writing process through the chipscope.
【CateGory Index】: TP333;TP273
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Chinese Journal Full-text Database 3 Hits
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