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《Modern Electronics Technique》 2007-03
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A Design of Locked Phase Programmable DPLL

LI Jianwei~1,XU Hongbing~1,WANG Yi~2(1.School of Automation Engineering,University of Electronic Science & Technology of China,,Chengdu,610054,China;2.Beijing Galleric Electronics Ltd.,Beijing,100081,China)  
At first,the paper introduces the structure and theory of typical All Digital Phase Locked Loop(ADPLL).Then it proposes a new design of ADPLL which can lock the input signals and output signals at multiple phase.It describes the design clue,structure and principle of the system.Verilog hardware description language is used to describe the design.Computer simulation,FPGA implementation and system board test all prove that the design is feasible.
【CateGory Index】: TN911.8
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