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《Journal of Zhejiang University(Engineering Science)》 2010-01
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ESD protection of NMOS device at different gate bias

ZHU Ke-han,DONG Shu-rong,HAN Yan,DU Xiao-yang(Department of Information Science and Electronic Engineering,Zhejiang University,Hangzhou 310027,China)  
In salicided sub-micron CMOS technology,the electrostatic discharge (ESD) performance of NMOS device as the self-protected output buffer at uncertain gate bias was analyzed.NMOS device structures for ESD protection were designed and fabricated in a 0.35 μm CMOS process.Their ESD abilities were measured by a transmission line pulse (TLP) testing system at different gate bias.With ISE-TCAD,the electric field density distribution of the device at different gate bias was shown by transient simulation.The results show that the gate bias can degrade the second breakdown current because of more current flow at the surface of NMOS device.When designing the snapback based gate coupled NMOS ESD protection device,the RC time constant of trigger-assisting circuit should be controlled around 50 ns.
【Fund】: 浙江省自然科学基金资助项目(Y107055 Y1080546)
【CateGory Index】: TN386
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【References】
Chinese Journal Full-text Database 2 Hits
1 HUANG Long;LIANG Hai-lian;GU Xiao-feng;DONG Shu-rong;BI Xiu-wen;WEI Zhi-fen;Key Laboratory of Advanced Process Control for Light Industry,Ministry of Education,Jiangnan University;Institute of Microelectronics and Optoelectronics,Zhejiang University;Xi'an XD Power Systems Co.,Ltd.;;Effect of poly-silicon gate on ESD protection performance of LDMOS-SCR devices[J];浙江大学学报(工学版);2015-02
2 LIANG Hai-lian;DONG Shu-rong;GU Xiao-feng;LI Ming-liang;HAN Yan;Key Laboratory of Advanced Process Control for Light Industry,Ministry of Education,Jiangnan University;Institute of Microelectronics and Optoelectronics,University;;ESD protection design of DDSCR structure based on the 0.5μm BCD process[J];浙江大学学报(工学版);2013-11
【Co-references】
Chinese Journal Full-text Database 2 Hits
1 ZHU Ke-han,DONG Shu-rong,HAN Yan,DU Xiao-yang(Department of Information Science and Electronic Engineering,Zhejiang University,Hangzhou 310027,China);ESD protection of NMOS device at different gate bias[J];浙江大学学报(工学版);2010-01
2 Li Meizhi and Chen Xingbi (School of Microelectronics and Solid-State Electronics,University of Electronic Science and Technology of China,Chengdu 610054,China);Influence of Gate Voltages on Temperature of LDMOS Under Ultra-High Transient Currents[J];半导体学报;2007-08
【Secondary References】
Chinese Journal Full-text Database 2 Hits
1 YAN Yongming;ZENG Yun;XIA Yu;ZHANG Guoliang;School of Physics and Microelectronics Science,Hunan University;;The Impact of Drift Implant on ESD Protection Performance of LDMOS-SCR ESD Device[J];固体电子学研究与进展;2015-06
2 Bi Xiuwen;Liang Hailian;Gu Xiaofeng;Huang Long;Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education), Department of Electronic Engineering,Jiangnan University;;Design of novel DDSCR with embedded PNP structure for ESD protection[J];Journal of Semiconductors;2015-12
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